As the digital processing core of the X300, the XC7K325T FPGA provides high-speed connectivity between all major components. Includes RF front end, host interface and DDR3 memory. The default FPGA provides all UHD for digital down conversion and digital up conversion, fine frequency tuning, and some other DSP function blocks. Users can take advantage of the rich space of the resource-rich Kintex-7 FPGA, plus the development framework supported by USRP, and open source projects to implement their own DSP processing modules.
Multiple High-Speed Interface Options
The X300 offers a variety of high speed interfaces to choose from. On the panel of the box, the Gigabit Ethernet port is the easiest way to interface. For applications that extend bandwidth and low latency, such as PHY/MAC research, PCIe x4 provides an efficient bus for this deterministic operation. When the application uses network recording or multi-node processing, the 10G port is the best choice.
Additional --GPSDO, GPIO, 1 GB DDR3
The X300 includes many additional features that will help with some other wireless applications. For example, in FPGA design, 1GB DDR3 on the motherboard can be used as data buffer and data storage. The optional internal GPSDO provides high-precision frequency reference when synchronized to the GPS system, and global timing alignment within 50ns. The external GPIO interface allows user-controlled external components such as amplifiers and switches to accept input event triggers and observe debug signals. The USRP-LW x300 also includes an internal JTAG adapter that allows FPGA developers to easily load and debug new FPGA images.
System and development environment
Included in This Equipment: